…coverage

…yte)

Merges 3 separate byte-level bitwise buses into 1 with op_type
discriminant. Reduces CPU interactions from 24 to 8, saving ~8 aux
columns. Affects CPU, bitwise, shift, and potentially memw_aligned tables.

Replace three separate BusId variants (AndByte=3, OrByte=4, XorByte=5)
with a single BitwiseByte=3 variant using an op_type discriminant field
(0=AND, 1=OR, 2=XOR). Renumber subsequent variants accordingly.

Replace three separate BusId::AndByte/OrByte/XorByte receivers with three
BitwiseByte receivers distinguished by a constant op_type field:
  AND receiver: op_type=0, OR receiver: op_type=1, XOR receiver: op_type=2

MU_AND, MU_OR, MU_XOR multiplicity columns remain separate and unchanged.
Adds LinearTerm to import.

Replace three separate 8-iteration loops (AND_BYTE, OR_BYTE, XOR_BYTE)
with a single merged loop over BitwiseByte using:
  - Multiplicity::Sum3(AND, OR, XOR)  (at most 1 active per cycle)
  - op_type field: 1*OR + 2*XOR (so AND=0, OR=1, XOR=2)

This reduces CPU bus interactions from 24 to 8. AND/OR/XOR are mutually
exclusive per cycle (enforced by DECODE), so Sum3 acts as a single active
multiplicity.

Update SHIFT-C1, SHIFT-C2, and SHIFT-C11 interactions from BusId::AndByte
to BusId::BitwiseByte, adding a constant op_type=0 (AND) as the 4th bus
field to match the merged bus protocol.

…type=0

Update the alignment-check bus interaction from BusId::AndByte to
BusId::BitwiseByte, adding a constant op_type=0 (AND) as the 4th field.

Update the PC alignment AND_BYTE interaction to BusId::BitwiseByte with
a constant op_type=0 (AND) as the 4th bus field.

Update standalone bus interaction tests in bitwise_bus_tests.rs and
bitwise_tests.rs to use BusId::BitwiseByte with a constant op_type=0
on both sender and receiver sides (both test AND operations). Add
LinearTerm to imports where missing.